M16C65 Datasheet, PDF (447/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
20.2.6 Real-Time Clock Control Register 2 (RTCCR2)
20. Real-Time Clock
Real-Time Clock Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RTCCR2
Address
0345h
After Reset
X000 0000b
Bit Symbol
Bit Name
Function
RW
0 : Disable periodic interrupt triggered
SEIE
Periodic interrupt triggered
every second enable bit
every second
1 : Enable periodic interrupt triggered
RW
every second
0 : Disable periodic interrupt triggered
MNIE
Periodic interrupt triggered
every minute enable bit
every minute
1 : Enable periodic interrupt triggered
RW
every minute
0 : Disable periodic interrupt triggered
HRIE
Periodic interrupt triggered
every hour enable bit
every hour
1 : Enable periodic interrupt triggered
RW
every hour
0 : Disable periodic interrupt triggered
DYIE
Periodic interrupt triggered
every day enable bit
every day
1 : Enable periodic interrupt triggered
RW
every day
0 : Disable periodic interrupt triggered
WKIE
Periodic interrupt triggered
every week enable bit
every week
1 : Enable periodic interrupt triggered
RW
every week
RTCCMP0
b6 b5
0 0 : No compare mode
RW
Compare mode select bit
0 1 : Compare 1 mode
RTCCMP1
1 0 : Compare 2 mode
1 1 : Compare 3 mode
RW
—
(b7)
No register bit. If necessary, set to 0. Read as undefined value
—
Write to the RTCCR2 register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer
stops).
While bits RTCCMP1 to RTCCMP0 are 00b (no compare mode), an interrupt request can be generated
every second, minute, hour, day, or week. To generate an interrupt request, set one of the following bits
to 1 (interrupt enabled): SEIE, MNIE, HRIE, DAYIE, and WKIE (Be sure to set only one bit to 1). Table
20.4 lists Periodic Interrupt Sources.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 412 of 791