M16C65 Datasheet, PDF (696/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
27. A/D Converter
27.3 Operations
27.3.1 A/D Conversion Cycle
A/D conversion cycle is based on fAD and φAD. Figure 27.2 shows fAD and φAD.
When the CKS3 bit in the ADCON2 register is 1 (fOCO40M is fAD), do not set the CKS2 bit in the
ADCON2 register to 0 and the CKS1 bit in the ADCON1 register to 1 (fDA = φAD).
Set the A/D converter related registers after setting the CKS3 bit.
0 ^CKS2
CKS3
f1 ⁰
fAD
fOCO40M
fAD ^1/3 ₁
1
CKS0: Bit in the ADCON0 register
CKS1: Bit in the ADCON1 register
CKS2, CKS3: Bits in the ADCON2 register
Figure 27.2 fAD and φAD
Figure 27.3 shows A/D Conversion Timing.
Select A/D conversion speed
CKS1
1
1
0
φAD
1/2
1/2
0
CKS0
Processing
cycle
Start
Open-circuit
processing _detection
Start
processing
Open-circuit
detection charge
time
1 to 2
fAD
2 φAD
First bit conversion time
Second bit Third bit
Sampling time
Compare Compare Compare
time
time
time
15 φAD
2.5 φAD
40 φAD
42 φAD
The above figure applies under the following conditions:
y One-shot mode
y φAD = fAD
Figure 27.3 A/D Conversion Timing
End
Tenth bit _processing
Compare End
time processing
2 to 3 fAD
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 661 of 791