M16C65 Datasheet, PDF (532/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
FER (Framing Error Flag) (b13)
The FER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
or to 010b (I²C mode). Read as undefined value.
Condition to become 0:
• Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
• The RE bit in the UiC1 register is 0 (reception disabled).
• The lower bytes of the UiRB register are read.
Condition to become 1:
• The set number of stop bits is not detected.
(detected when the received data is transferred from the UARTi receive register to the UiRB
register.)
PER (Parity Error Flag) (b14)
The PER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
or to 010b (I²C mode). Read as undefined value.
Condition to become 0:
• Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
• The RE bit in the UiC1 register is 0 (reception disabled).
• The lower bytes of the UiRB register are read.
Condition to become 1:
• The number of 1s of the parity bit and character bit does not match the set value of the PRY bit in
the UiMR register.
(detected when the received data is transferred from the UARTi receive register to the UiRB
register.)
SUM (Error Sum Flag) (b15)
The SUM bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode)
or to 010b (I²C mode). Read as undefined value.
Condition to become 0:
• Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled).
• The RE bit in the UiC1 register is 0 (reception disabled).
• All of bits PER, FER and OER are 0 (no error).
Condition to become 1:
• More than one of bits PER, FER or OER is 1 (error found).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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