M16C65 Datasheet, PDF (640/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.7 Start Condition and Stop Condition Detection
Figure 25.13 shows Start Condition Detection, Figure 25.14 shows Stop Condition Detection, and Table
25.14 lists Conditions to Detect Start/Stop Condition.
Start/Stop condition is detected only when the start/stop condition detect conditions (SCL open time,
setup time, and hold time) are selected by bits SSC4 to SSC0 in the S2D0 register, and the signals
input to pins SCLMM and SDAMM meet all three conditions (SCLMM open time, setup time, and hold
time) listed in Table 25.14.
The BB bit in the S10 register becomes 1 when a start condition is detected. It becomes 0 when a stop
condition is detected. The set timing and reset timing of the BB bit depends on the mode, standard
mode or high-speed clock mode. Refer to BB bit set/reset time in Table 25.15.
Table 25.15 lists Recommended SSCi (i = 0 to 4) Bit Value in Standard Clock Mode.
SCLMM
SDAMM
BB bit in the S10 register
TRX bit in the S10 register
Bits BC2 to BC0 in the S1D0 register
SCLMM open
Setup
Hold
Setting BB bit
Figure 25.13 Start Condition Detection
(In slave mode)
000b
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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