M16C65 Datasheet, PDF (350/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
17.3.4.3 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to 0000h by Z-phase (counter initialization) input during
two-phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal
processing, free-running type, multiply-by-4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing 0000h to the TA3 register and setting the
TAZIE bit in the ONSF register to 1 (Z-phase input enabled).
Counter initialization is accomplished by Z-phase input edge detection. The rising or falling edge can
be selected as the active edge by using the POL bit in the INT2IC register. The Z-phase pulse width
applied to the ZP pin must be equal to or greater than one clock cycle of timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 17.9 shows
the Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase.
If timer A3 overflow or underflow coincides with counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
ZP ⁽¹⁾
Timer A3
Input equal to or greater than one clock cycle
of count source
m m+1 1
2
3
4
5
Note :
1. This timing diagram applies when the POL bit in the INT2IC register is 1 (rising edge).
Figure 17.9 Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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