M16C65 Datasheet, PDF (258/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.2.2
Interrupt Control Register 1
(TB5IC, TB4IC/U1BCNIC, TB3IC/U0BCNIC, BCNIC, DM0IC to DM3IC, KUPIC,
ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC to TB2IC,
U5BCNIC/CEC1IC, S5TIC/CEC2IC, S5RIC to S7RIC, U6BCNIC/RTCTIC,
S6TIC/RTCCIC, U7BCNIC/PMC0IC, S7TIC/PMC1IC, IICIC, SCLDAIC)
Interrupt Control Register 1
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
TB5IC
TB4IC/U1BCNIC
TB3IC/U0BCNIC
BCNIC
DM0IC to DM3IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
U5BCNIC/CEC1IC
S5TIC/CEC2IC
S5RIC to S7RIC
U6BCNIC/RTCTIC
S6TIC/RTCCIC
U7BCNIC/PMC0IC
S7TIC/PMC1IC
IICIC
SCLDAIC
Address
0045h
0046h
0047h
004Ah
004Bh, 004Ch, 0069h, 006Ah
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
006Bh
006Ch
006Dh, 0070h, 0073h
006Eh
006Fh
0071h
0072h
007Bh
007Ch
After Reset
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
Bit Symbol
Bit Name
Function
RW
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
RW
0 0 1 : Level 1
ILVL1
Interrupt priority level select
bit
0
0
1
1
1
0
0 : Level 2
1 : Level 3
0 : Level 4
RW
1 0 1 : Level 5
ILVL2
1 1 0 : Level 6
RW
1 1 1 : Level 7
IR
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
RW
—
(b7-b4)
No register bits. If necessary, set to 0. Read as undefined value
—
Rewrite this register at a point that does not generate an interrupt request.
When multiple interrupt sources share the register, select an interrupt source in registers IFSR2A and
IFSR3A.
IR (Interrupt Request Bit) (b3)
The IR bit can only be set to 0 (do not write 1).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 223 of 791