M16C65 Datasheet, PDF (546/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1) Example of Transmit Timing (Internal Clock Selected)
Tc
Transmit/receive clock
TE bit in
UiC1 register
TI bit in
UiC1 register
CTSi
CLKi
1
0
1
0
High
Low
Set the data in the UiTB register.
TCLK
Data is transferred from the UiTB register to
the UARTi transmit register.
Pulse stops because a high-
level signal is applied to CTSi
Pulse stops because the TE bit is set to 0
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPT flag in
1
UiC0 register
0
IR bit in
1
SiTIC register
0
i = 0 to 2, 5 to 7
Set to 0 by an interrupt request acknowledgement or by a program.
The above timing diagram applies when the register bits are set as follows:
· The CKDIR bit in the UiMR register = 0 (internal clock)
· The CRD bit in the UiC0 register = 0 (CTS/RTS enabled), the CRS bit = 0 (CTS selected)
· The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transmit/receive clock)
· The UiIRS bit in the UiC1 register = 0 (an interrupt request occurs when the UiTB register
becomes empty)
T_C = T_CLK = 2(n + 1)/fj
fj: Frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: Value set to the UiBRG register
(2) Example of Receive Timing (External Clock Selected)
RE bit in
1
UiC1 register
0
TE bit in
UiC1 register
TI bit in
UiC1 register
RTSi
CLKi
RXDi
RI bit in
UiC1 register
1
0
1
0
High
Low
1
0
Set the dummy data in the UiTB register.
Data is transferred from the UiTB register to the UARTi transmit register.
1/fEXT
A low-level signal is applied when the UiRB register is read.
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
Data is transferred from the UARTi
receive register to the UiRB register
Read the UiRB register
IR bit in
1
SiRIC register
0
OER flag in
1
UiRB register
0
i = 0 to 2, 5 to 7
Set to 0 by an interrupt request acknowledgement or by a program.
The above timing diagram applies to the case where the register bits are set as follows:
· The CKDIR bit in the UiMR register = 1 (external clock)
· The CRD bit in the UiC0 register = 0 (CTS/RTS enabled), the CRS bit = 1 (RTS selected)
· The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transmit/
receive clock)
fEXT: Frequency of the external clock
Make sure the following conditions are met when input to
the CLKi pin before receiving data is high:
· The TE bit in the UiC1 register = 1 (transmit enabled)
· The RE bit in the UiC1 register = 1 (receive enabled)
· Write dummy data to the UiTB register
Figure 23.5 Transmit/Receive Operation during Clock Synchronous Serial I/O Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 511 of 791