M16C65 Datasheet, PDF (257/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14.2.1 Processor Mode Register 2 (PM2)
14. Interrupts
Processor Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM2
Address
001Eh
After Reset
XX00 0X01b
Bit Symbol
Bit Name
Function
RW
PM20
Specifying wait when accessing 0 : 2 waits
SFR at PLL operation
1 : 1 wait
RW
PM21 System clock protection bit
0 : Clock is protected by PRCR register
1 : Clock change disabled
RW
—
(b2)
No register bit. If necessary, set to 0. Read as 0
—
—
(b3)
Reserved bit
Set to 0
RW
PM24 NMI interrupt enable bit
0 : NMI interrupt disabled
1 : NMI interrupt enabled
RW
PM25
Peripheral clock fC provide bit
0 : Provided
1 : Not provide
RW
—
(b7-b6)
No register bits. If necessary, set to 0. Read as undefined value
—
Set the PRC1 bit in the PRCR register to 1 (write enabled) before the PM2 register is rewritten.
PM24 (NMI Interrupt Enable Bit) (b4)
Once this bit is set to 1, it cannot be set to 0 by a program (writing a 0 has no effect).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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