M16C65 Datasheet, PDF (367/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
17.5.3 Timer A (One-Shot Timer Mode)
17.5.3.1 Register Setting
The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR
register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register,
registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR register
before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4).
Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR
register, registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR
register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not.
17.5.3.2 Stop While Counting
When setting the TAiS bit to 0 (count stops), the following occurs:
• The counter stops counting and the contents of the reload register are reloaded.
• The TAiOUT pin outputs a low-level signal when the POFSi bit in the TAPOFS register is 0 and out-
puts a high-level signal when it is 1.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to 1 (interrupt requested).
17.5.3.3 Delay between the Trigger Input and Timer Output
One-shot timer output synchronizes with a count source generated internally. When an external
trigger is selected, a maximum 1.5 cycle delay of the count source occurs between the trigger input to
the TAiIN pin and timer output.
17.5.3.4 Operating Mode Change
The IR bit is set to 1 when timer operating mode is set with any of the following procedures:
• Selecting one-shot timer mode after reset
• Changing the operating mode from timer mode to one-shot timer mode
• Changing the operating mode from event counter mode to one-shot timer mode
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after the changes listed above are made.
17.5.3.5 Re-Trigger
When a trigger occurs while counting, the counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, generate
a re-trigger after more than one cycle of the timer count source has elapsed following the previous
trigger.
When an external trigger occurs, do not generate a re-trigger for 300 ns before the count value
becomes 0000h.
The one-shot timer may stop counting.
17.5.3.6 Influence of SD
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT
enter a high-impedance state.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 332 of 791