M16C65 Datasheet, PDF (250/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
13. Programmable I/O Ports
13.4.3 NMI/SD Digital Filter
The NMI/SD input circuit includes a digital filter. Sampling clock can be selected by bits NMIDF2 to
NMIDF0 in the NMIDF register. The NMI level is sampled for every sampling clock. When the same
sampled level is detected three times in a row, the level is transferred to the internal circuit.
When using the NMI/SD digital filter, do not enter wait mode or stop mode.
Port P8_5 is not affected by the digital filter.
When using the CEC function, set bits NMIDF2 to NMIDF0 to 000b (NMI/SD digital filter disabled).
Figure 13.11 shows NMI/SD Digital Filter, and Figure 13.12 shows NMI/SD Digital Filter Operation
Example.
NMIDF2 to NMIDF0
CPU clock
Sampling clock
Divider
P8_5/NMI/SD/CEC
Digital Filter
NMIDF2 to NMIDF0
Other than 000b
000b
PM24
PM24: Bit in the PM2 register
NMIDF2 to NMIDF0: Bits in the NMIDF register
Figure 13.11 NMI/SD Digital Filter
NMI interrupt
SD input
CEC input
P8_5 input
Sampling timing
NMI/SD pin
NMI/SD input
3 levels agreed
NMI interrupt is generated when the PM 24 bit
in the PM2 register is 1 (NMI interrupt enabled).
Note that the above applies when bits NMIDF2 to NMIDF0 in the NMIDF register are set to a value
other than 000b (NMI/SD filter enabled).
Figure 13.12 NMI/SD Digital Filter Operation Example
13.4.4 CNVSS
The built-in pull-up resistor of the CNVSS pin is activated after watchdog timer reset, hardware reset,
power-on reset or voltage monitor 0 reset. Thus, the CNVSS pin outputs a high-level signal up to two
cycles of the fOCO-S. Connect the CNVSS pin to VSS via a resistor to use it in single-chip mode.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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