M16C65 Datasheet, PDF (755/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
30. Flash Memory
30.8.5.3 Program Status (Bits SR4 and FMR06)
The program status indicates auto-program operating state.
Condition to become 0:
• Execute the clear status command
Condition to become 1:
• Refer to 30.8.5.4 “Full Status Check”.
When the FMR06 bit is 1, the following commands cannot be accepted:
Program, block erase, lock bit program, read lock bit status, block blank check
30.8.5.4 Full Status Check
If an error occurs, bits FMR06 and FMR07 in the FMR0 register are set to 1, indicating the
occurrence of an error. Therefore, the execution results can be confirmed by checking these status
bits (full status check).
Table 30.16 lists Errors and FMR0 Register States and Figure 30.8 shows Full Status Check and
Handling Procedure for Errors.
Table 30.16 Errors and FMR0 Register States
FMR00 Register
(Status Register) State
FMR07 bit FMR06 bit
Error
Error Occurrence Conditions
(SR5 bit)
(SR4 bit)
Command Sequence • Command is written incorrectly.
error
1
1
• Invalid data (data other than xxD0h or xxFFh)
is written in the second bus cycle of the lock bit
program or block erase command. ⁽¹⁾
Erase error
• The block erase command is executed on a
locked block. ⁽²⁾
• The block erase command is executed on an
1
0
unlocked block, but the auto-erase operation is
not completed as expected.
• The block blank check command is executed,
and the check result is not blank.
Program error
• The program command is executed on a
locked block. ⁽²⁾
• The program command is executed on an
0
1
unlocked block, but auto-program operation is
not completed as expected.
• The lock bit program command is executed,
but the lock bit is not written as expected. ⁽²⁾
Notes:
1. The flash memory enters read array mode by writing command code xxFFh in the second bus
cycle of the command. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to 1 (lock bit disabled), no error occurs even under the conditions
above.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 720 of 791