M16C65 Datasheet, PDF (642/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
Table 25.14 Conditions to Detect Start/Stop Condition
Standard Clock Mode
SCLMM open time SSC value + 1 cycle
Setup time
S_----S_----C_-------v_---a_---l_-u_----e_{- + 1 cycles}
2
High-speed Clock Mode
4 cycles
2 cycles
Hold time
S-----S----C-----v----a---l-u----e- _cycles
2
2 cycles
BB bit set/ reset
time
S_-----S_----C_-----v_----a_---l_-u_----e_{----–-----1- + 2 cycles}
2
3.5 cycles
Unit: fVIIC cycles
SSC value: Value of bits SSC4 to SSC0 in the S2D0 register
Table 25.15 Recommended SSCi (i = 0 to 4) Bit Value in Standard Clock Mode
fVIIC
SSC Value Start/stop Condition
(recommen _{SCLMM Open}
ded)
Time
Setup Time
Hold Time
BB Bit Set/reset
Time
5 MHz 11110b
6.2 μs (31)
3.2 μs (16)
3.0 μs (15)
4.125 μs (16.5)
4 MHz 11010b 6.75 μs (27)
3.5 μs (14)
3.25 μs (13)
3.625 μs (14.5)
11000b 6.25 μs (25)
3.25 μs (13)
3.0 μs (12)
3.375 μs (13.5)
2 MHz 01100b 6.5 μs (13)
3.5 μs (7)
3.0 μs (6)
3.75 μs (7.5)
01010b 5.5 μs (11)
3.0 μs (6)
2.5 μs (5)
3.25 μs (6.5)
1 MHz 00100b 5.0 μs (5)
3.0 μs (3)
2.0 μs (2)
3.5 μs (3.5)
SSC value: Value of bits SSC4 to SSC0 in the S2D0 register
( ): fVIIC cycles
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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