M16C65 Datasheet, PDF (643/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.8 Operation After Completion of Slave Address/Data Transmit/Receive
After completing transmission/reception of slave address or one-byte data, the PIN bit in the S10
register is set to 0 (interrupt requested) at the falling edge of ACK clock. The IR bit in the IICIC register
becomes 1 (interrupt requested) at the same time. The value in the S10 register and so on changes
depending on the state of transmit/receive data, and the level of pins SCLMM and SDAMM. Figure
25.15 shows Operation After Completion of Slave Address/Data Transmit/Receive.
SCLMM
ACK clock
SCLMM pin outputs low
when PIN bit is 0
SDAMM
PIN bit in the
S10 register
Bits BC2 to BC0 in
the S1D0 register
MST bit in the
S10 register
TRX bit in the
S10 register
TRX bit in the
S10 register
ADR0 bit in the
S10 register
AAS bit in the
S10 register
IR bit in the IICIC
register
A/A
000b
(When arbitration is lost)
(When no ACK is returned in
slave transmit mode)
2 fVIIC cycles
(R/W bit is set to 1 in slave
address receive mode
1 fVIIC cycles
(General call in slave
address receive mode)
(General call address or
normal address matches
in slave address receive
mode)
Set to 0 by an interrupt request acceptance
or by a program
Figure 25.15 Operation After Completion of Slave Address/Data Transmit/Receive
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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