M16C65 Datasheet, PDF (617/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25.2.7 I2C0 Control Register 1 (S3D0)
25. Multi-Master I²C-bus Interface
I2C0 Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3D0
Address
02B6h
After Reset
0011 0000b
Bit Symbol
Bit Name
Function
RW
SIM
WIT
PED
0: I²C-bus interrupt by stop condition
Stop condition detect interrupt detection is disabled
enable bit
1: I²C-bus interrupt by stop condition
RW
detection is enabled
When write,
0: I²C-bus interrupt at 8th clock is disabled
Data receive interrupt enable
bit
1: I²C-bus interrupt is enabled at 8th clock
When read, internal WAIT bit monitor
RW
0: I²C-bus interrupt by falling edge of ACK clock
1: I²C-bus interrupt at 8th clock
SDAMM/port function select 0: SDAMM I/O pin
bit
1: Port output pin
RW
PEC
SCLMM/port function select bit
0: SCLMM I/O pin
1: Port output pin
RW
SDAM
Internal SDA output monitor
bit
0: Logic 0 output
1: Logic 1 output
RO
SCLM
Internal SCL output monitor bit
0: Logic 0 output
1: Logic 1 output
RO
ICK0
I2C-bus system clock select
bit
b7 b6
0 0: fIIC divided by 2
RW
(Enabled when bits ICK4 to 0 1: fIIC divided by 4
ICK1
ICK2 in the S4D0 register are 1 0: fIIC divided by 8
000b)
1 1: Should not be set
RW
Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register. Use
MOV instruction to write to the S3D0 register.
SIM (Stop Condition Detect Interrupt Enable Bit) (b0)
When the SIM bit is 1 (I²C-bus interrupt by stop condition detection enabled) and a stop condition is
detected, the SCPIN bit in the S4D0 register becomes 1 (stop condition detect interrupt requested) and
the IR bit in the IICIC register becomes 1 (interrupt requested).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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