M16C65 Datasheet, PDF (575/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.4.1 Clock Phase Setting Function
One of four combinations of transmit/receive clock phases and polarities can be selected using the
CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transmit/receive clock polarity and phase are the same for the master and salve
devices to be used for communication.
Figure 23.23 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 23.24 shows the Transmission and Reception Timing (CKPH = 0) in Slave Mode (External
Clock) while Figure 23.25 shows the Transmission and Reception Timing (CKPH = 1) in Slave Mode
(External Clock).
Clock output
High
(CKPOL = 0, CKPH = 0) Low
Clock output
High
(CKPOL = 1, CKPH = 0) _Low
Clock output
High
(CKPOL = 0, CKPH = 1) _Low
Clock output
High
(CKPOL = 1, CKPH = 1) _Low
Data output timing
High
Low
Data input timing
D0 D1 D2 D3 D4 D5 D6 D7
Figure 23.23 Transmission and Reception Timing in Master Mode (Internal Clock)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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