M16C65 Datasheet, PDF (529/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.1 UART Clock Select Register (UCLKSEL0)
UART Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
UCLKSEL0
Address
0252h
After Reset
X0h
Bit Symbol
Bit Name
Function
RW
—
(b1-b0)
Reserved bits
Set to 0
RW
OCOSEL0
Clock select prior to UART0
to UART2 division bit
0 : f1
1 : fOCO-F
RW
OCOSEL1
Clock select prior to UART5
to UART7 division bit
0 : f1
1 : fOCO-F
RW
—
(b7-b4)
No register bits. If necessary, set to 0. Read as undefined value
—
OCOSEL0 (Clock Select Prior to UART0 to UART2 Division Bit) (b2)
OCOSEL1 (Clock Select Prior to UART5 to UART 7 Division Bit) (b3)
Set bits OCOSEL0 and OCOSEL1 while transmission/reception of UART0 to UART2 and UART5 to
UART7 stops.
Set the OCOSEL0 or OCOSEL1 bit before setting other registers associated with UART0 to UART2
and UART5 to UART7. After changing the OCOSEL0 or OCOSEL1 bit, set other registers associated
with UART0 to UART2 and UART5 to UART7 again.
23.2.2 Peripheral Clock Select Register (PCLKR)
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
00 000
Symbol
PCLKR
Address
0012h
After Reset
0000 0011b
Bit Symbol
Bit Name
Function
RW
Timers A and B clock select bit
PCLK0
(clock source for timers A and
B, the dead time timer, and
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
RW
muliti-master I²C-bus interface)
SI/O clock select bit
PCLK1
(clock source for UART0 to
UART2, UART5 to UART7,
0: f2SIO
1: f1SIO
RW
SI/O3, and SI/O4)
—
(b4-b2)
Reserved bits
Set to 0
RW
Clock output function
0: Selected by bits CM01 to CM00
PCLK5 extension bit
in the CM0 register
RW
(valid in single-chip mode)
1: Output f1
—
(b7-b6)
Reserved bits
Set to 0
RW
Set the PRC0 bit in the PRCR register to 1 (write enabled) before the PCLKR register is rewritten.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 494 of 791