M16C65 Datasheet, PDF (218/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
12.2.1 Data Bank Register (DBR)
12. Memory Space Expansion Function
Data Bank Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DBR
Address
000Bh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
—
(b1-b0)
No register bits. If necessary, set to 0. Read as 0
—
OFS Offset bit
0 : No offset
1 : Offset
RW
BSR0
BSR1 Bank select bit
BSR2
RW
b5 b4 b3
b5 b4 b3
0 0 0 : Bank 0 0 0 1 : Bank 1
0 1 0 : Bank 2 0 1 1 : Bank 3
RW
1 0 0 : Bank 4 1 0 1 : Bank 5
1 1 0 : Bank 6 1 1 1 : Bank 7
RW
—
(b7-b6)
No register bits. If necessary, set to 0. Read as 0
—
The DBR register is valid when bits PM01 to PM00 in the PM0 register are 01b (memory expansion
mode) or 11b (microprocessor mode).
A write to the DBR register is enabled when bits PM15 to PM14 in the PM1 register is 11b (4-Mbyte
mode).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 183 of 791