M16C65 Datasheet, PDF (566/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
In I²C mode, the functions and timings vary depending on the combination of the IICM2 bit in the
UiSMR2 register and CKPH bit in the UiSMR3 register. Figure 23.19 shows Transfer to UiRB
Register and Interrupt Timing. Refer to Figure 23.19 for the timing of transferring to the UiRB register,
the bit position of the data stored in the UiRB register, types of interrupts, interrupt requests and DMA
request generation timing.
Table 23.18 “I²C Mode Functions” lists comparison of other functions in clock synchronous serial I/O
mode with I²C mode.
Table 23.18 I²C Mode Functions
Function
Clock Synchronous Serial
I/O Mode (SMD2 to SMD0
= 001b, IICM = 0)
I²C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK Interrupt)
IICM2 = 1
(UART Transmit/Receive Interrupt)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Start and stop condition
-
detection interrupts
Start condition detection or stop condition detection
(See Figure 23.21 “STSPSEL Bit Functions”)
Transmission, NACK
interrupt ⁽²⁾
UARTi transmission
Transmission started or
completed (selected by
UiIRS)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
UARTi transmission
Rising edge of SCLi
9th bit
UARTi transmission
Falling edge of SCLi
next to the 9th bit
Reception, ACK interrupt ⁽²⁾
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Timing for transferring data
from UART reception shift
register to UiRB register
CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit
CKPOL = 1 (falling edge)
Falling edge of SCLi Falling and rising
9th bit
edges of SCLi 9th bit
UARTi transmission output Not delayed
delay
Delayed
Noise filter width
15 ns
200 ns
Read RXDi and SCLi pin
levels
Possible when the
corresponding port
direction bit = 0
Always possible no matter how the corresponding port direction bit is set
Initial value of TXDi and
SDAi outputs
CKPOL = 0 (high)
CKPOL = 1 (low)
The value set in the port register before setting I²C mode ⁽¹⁾
Initial and end values of
-
SCLi
High
Low
High
Low
DMA1, DMA3 Factor ⁽²⁾
UARTi reception
Acknowledgment detection (ACK)
UARTi reception
Falling edge of SCLi 9th bit
Read received data
1st to 8th bits of the
received data are stored
in bits 0 to 7 in the UiRB
register.
1st to 8th bits of the received data are
stored in bits 7 to 0 in the UiRB register.
1st to 7th bits of the
received data are
stored in bits 6 to 0
in the UiRB register.
8th bit is stored into
bit 8 in the UiRB
register.
When reading by
reception interrupt, 1st
to 7th bits of the
received data are
stored in bits 6 to 0 in
the UiRB register. 8th
bit is stored into bit 8 in
the UiRB register.
When reading by
transmission interrupt,
1st to 8th bits are
stored into bits 7 to 0
in the UiRB register.
i = 0 to 2, 5 to 7
Notes:
1. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register are 000b (serial interface
disabled).
2. See Figure 23.19 “Transfer to UiRB Register and Interrupt Timing”.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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