M16C65 Datasheet, PDF (541/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.12 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7)
UARTi Special Mode Register 3 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3, U1SMR3, U2SMR3
U5SMR3, U6SMR3, U7SMR3
Address
0245h, 0255h, 0265h
0285h, 0295h, 02A5h
Bit Symbol
Bit Name
Function
After Reset
000X 0X0Xb
000X 0X0Xb
RW
—
(b0)
No register bit. If necessary, set to 0. Read as undefined value
—
CKPH Clock phase set bit
0 : No clock delay
1 : With clock delay
RW
—
(b2)
No register bit. If necessary, set to 0. Read as undefined value
—
NODC Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
—
(b4)
No register bit. If necessary, set to 0. Read as undefined value
—
DL0
DL1
SDAi digital delay
setup bit
DL2
b7 b6 b5
0 0 0 : No delay
RW
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source RW
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
RW
NODC (Clock Output Select Bit) (b3)
This function is used to set P-channel transistor of the COMS output buffer always off, but not to
change the CLKi pin to open-drain output completely.
Check electrical characteristics for the input voltage range.
DL2-DL0 (SDAi Digital Delay Setup Bit) (b7-b5)
Bits DL2 to DL0 are used to generate a delay in SDAi output by digital means in I²C mode. Except for
I²C mode, set these bits to 000b (no delay).
The amount of delay varies with the load on pins SCLi and SDAi. Also, when using an external clock,
the amount of delay increases by about 100 ns.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 506 of 791