M16C65 Datasheet, PDF (559/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.2.4 Serial Data Logic Switching Function
The logic of the data written to the UiTB register is reversed and then transmitted. Similarly, the
reversed logic of the received data is read when the UiRB register is read. Figure 23.15 shows Serial
Data Logic.
(1) UiLCH bit in the UiC1 register = 0 (no reverse)
Transmit/
High
receive clock
Low
TXDi
High
(no reverse)
Low
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) UiLCH bit in the UiC1 register = 1 (reverse)
Transmit/
High
receive clock
Low
TXDi
High
(reverse)
Low
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2, 5 to 7
The above applies under the following conditions.
- The CKPOL bit in the UiC0 register is0 (transmit data output at the falling edge of
the transmit/receive clock).
- The UFORM bit in the UiC0 register is 0 (LSB first).
- The STPS bit in the UiMR register is 0 (1 stop bit).
- The PRYE bit in the UiMR register is 1 (parity enabled).
- The IOPOL bit in the UiMR register is 0 (TXD, RXD I/O not reversed).
Figure 23.15 Serial Data Logic
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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