M16C65 Datasheet, PDF (587/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.5.1.3 Reception
In clock synchronous serial I/O mode, the shift clock is generated by activating a transmitter. Set the
UARTi-associated registers for a transmit operation even if the MCU is used for receive operation
only. Dummy data is output from the TXDi pin (i = 0 to 2, 5 to 7) while receiving.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the UiC1
register to 1 (transmission enabled) and placing dummy data in the UiTB register. When an external
clock is selected, set the TE bit to 1 (transmission enabled), place dummy data in the UiTB register,
and input an external clock to the CLKi pin to generate the shift clock.
If data is received consecutively, an overrun error occurs when the RI bit in the UiC1 register is set to
1 (data present in the UiRB register) and the next receive data is received in the UARTi receive
register. And then, the OER bit in the UiRB register is set to 1 (overrun error occurred). At this time,
the UiRB register is undefined. When an overrun error occurs, program the transmitting and receiving
sides to retransmit the previous data. If an overrun error occurs, the IR bit in the SiRIC register
remains unchanged.
To receive data consecutively, set dummy data in the low-order byte in the UiTB register per each
receive operation.
When an external clock is selected, the following conditions must be met while the external clock is
held high when the CKPOL bit is 0 (transmit data output at the falling edge and receive data input at
the rising edge of the serial clock), or while the external clock is held low when the CKPOL bit is 1
(transmit data output at the rising edge and receive data input at the falling edge of the serial clock).
• The RE bit in the UiC1 register is 1 (reception enabled).
• The TE bit in the UiC1 register is 1 (transmission enabled).
• The TI bit in the UiC1 register is 0 (data present in the UiTB register).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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