M16C65 Datasheet, PDF (333/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17.2.12 Trigger Select Register (TRGSR)
17. Timer A
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0323h
Bit Symbol
Bit Name
Timer A1 event/trigger
TA1TGL _{select bit}
TA1TGH
Timer A2 event/trigger
TA2TGL _{select bit}
TA2TGH
Timer A3 event/trigger
TA3TGL _{select bit}
TA3TGH
Timer A4 event/trigger
TA4TGL _{select bit}
TA4TGH
Function
b1 b0
0 0 : Input on TA1IN selected
0 1 : TB2 selected
1 0 : TA0 selected
1 1 : TA2 selected
b3 b2
0 0 : Input on TA2IN selected
0 1 : TB2 selected
1 0 : TA1 selected
1 1 : TA3 selected
b5 b4
0 0 : Input on TA3IN selected
0 1 : TB2 selected
1 0 : TA2 selected
1 1 : TA4 selected
b7 b6
0 0 : Input on TA4IN selected
0 1 : TB2 selected
1 0 : TA3 selected
1 1 : TA0 selected
After Reset
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
TA1TGH-TA1TGL (Timer A1 Event/Trigger Select Bit) (b1-b0)
TA2TGH-TA2TGL (Timer A2 Event/Trigger Select Bit) (b3-b2)
TA3TGH-TA3TGL (Timer A3 Event/Trigger Select Bit) (b5-b4)
TA4TGH-TA4TGL (Timer A4 Event/Trigger Select Bit) (b7-b6)
These bits are used to select an event or a trigger of the following modes:
• Event in event counter mode (not using two-phase pulse signal processing)
• Trigger in one-shot timer mode, PWM mode, or programmable output mode
The above applies when the MR2 bit in the TAiMR register is 1 (trigger selected by bits TAiTGH to
TAiTGL).
The active edge of input signals can be selected by the MR1 bit in the TAiMR register when bits
TAiTGH to TAiTGL are 00b.
When bits TAiTGH to TAiTGL are set to 01b, 10b, or 11b, an event or a trigger occurs when an interrupt
request of the selected timer is generated. (An event or a trigger occurs while an interrupt is disabled
because bits TAiTGH to TAiTGL are not influenced by I flag, IPL, or the interrupt control registers.)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 298 of 791