M16C65 Datasheet, PDF (497/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
22.3 Operations
22.3.1 Common Operations in Multiple Modes
22.3.1.1 Count Source
Clock source and divisor of the count source can be selected by bits CSRC1 to CSRC0 and bits
CDIV1 to CDIV0 in the PMCiCON3 register (Refer to Figure 22.3 “Remote Control Signal Receiver
Block Diagram (3/3) (PMCi Count Source)”).
When using fC, set the PM25 bit in the PM2 register to 1 (peripheral clock fC provided). Refer to 8.
“Clock Generator” for details of fC.
When using timer B1 or B2 underflow, the internal signal of a timer B1 or B2 is inverted every time the
timer B1 or B2 underflows. This internal signal is the count source. One cycle of the count source
consists of two timer B1 or B2 underflow cycles. Figure 22.4 shows Clock Source When Selecting
Timer B1 or B2 Underflow. Use the timer B1 or B2 in timer mode. Refer to 18. “Timer B” for details.
Count source
(timer B2 internal signal)
Timer B2
underflow
cycle
Timer B2
underflow
cycle
Inverted by underflow
Clock source cycle
The above diagram shows an instance of timer B2
Operation is the same in timer B1.
Figure 22.4 Clock Source When Selecting Timer B1 or B2 Underflow
To use the same count source in PMC0 and PMC1, set bits CSRC1 to CSRC0 in the PMC0CON3 register
to 00b (same count source as PMC1), and bits CDIV1 to CDIV0 in the PMC0CON3 register to 00b (no
division).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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