M16C65 Datasheet, PDF (142/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8.2.4 Oscillation Stop Detection Register (CM2)
8. Clock Generator
Oscillation Stop Detection Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
CM2
Address
000Ch
After Reset
0X00 0010b
Bit Symbol
Bit Name
Function
RW
CM20
Oscillation stop and
re-oscillation detection enable
bit
0: Oscillation stop and re-oscillation
detection function disabled
1: Oscillation stop and re-oscillation
detection function enabled
RW
CM21 System clock select bit 2
0: Main clock or PLL clock
1: On-chip oscillator clock
RW
CM22
Oscillation stop and
re-oscillation detection
flag
0: Main clock stopped and re-oscillation
not detected
1: Main clock stopped and re-oscillation
RW
detected
CM23 XIN monitor flag
0: Main clock oscillating
1: Main clock stopped
RO
—
(b5-b4)
Reserved bits
Set to 0
RW
—
(b6)
No register bit. If necessary, set to 0. Read as undefined value
—
Operation select bit
0: Oscillation stop detection reset
CM27 (when an oscillation stop or 1: Oscillation stop/re-oscillation detection RW
re-oscillation is detected)
interrupt
Rewrite the CM2 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Bits
CM20, CM21, and CM27 do not change at oscillation stop detection reset.
Refer to Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode.
CM20 (Oscillation Stop and Re-Oscillation Detection Enable Bit) (b0)
Set the CM20 bit to 0 (oscillation stop and re-oscillation detection function disabled) to enter stop mode.
Set the CM20 bit back to 1 (enabled) after stop mode is exited.
When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM20 bit remains unchanged
even when being written.
CM21 (System Clock Select Bit 2) (b1)
When the CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock used as CPU clock source),
the CPU clock source and the peripheral function clock f1 can be selected by the CM21 bit. When the
CM07 bit is 1 (sub clock used as CPU clock source), the peripheral function clock f1 can be selected by
the CM21 bit.
To set the CM21 bit to 1 (on-chip oscillator clock), set the FRA01 bit in the FRA0 register to select either
the 125 kHz on-chip oscillator, or the 40 MHz on-chip oscillator.
When the CM20 bit is 1 (oscillation stop and re-oscillation detection function enabled) and the CM23 bit
is 1 (main clock stopped), do not set the CM21 bit to 0 (main clock or PLL clock).
When the CM20 bit is 1 (oscillation stop and re-oscillation detection function enabled), the CM27 bit is 1
(oscillation stop and re-oscillation detection interrupt), and the main clock is used as a CPU clock
source, the CM21 bit is automatically set to 1 (on-chip oscillator clock) if main clock stop is detected.
See 8.7 “Oscillation Stop/Re-Oscillation Detect Function” for details.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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