M16C65 Datasheet, PDF (206/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
11.3.5.6 RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If
input to the RDY pin is low at the last falling edge of BCLK in the bus cycle, one wait state is inserted
in the bus cycle. While in wait state, the following signals retain the state in which they were when the
RDY signal was acknowledged:
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when input to the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 11.4 shows Examples in Which Wait State Was Inserted into Read Cycle by RDY
Signal. To use the RDY signal, set the corresponding bit (among bits CS3W to CS0W) in the CSR
register to 0 (with wait state). When not using the RDY signal, pull-up the RDY pin.
Separate bus
BCLK
RD
CSi
(i = 0 to 3)
RDY
tsu (RDY-BCLK)
Multiplexed bus
Accept timing of RDY signal
BCLK
RD
CSi
(i = 0 to 3)
RDY
tsu (RDY-BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
tsu (RDY - BCLK) : Duration for RDY input setup
Shown above is a case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are
00b (one wait state).
Figure 11.4 Examples in Which Wait State Was Inserted into Read Cycle by RDY Signal
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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