M16C65 Datasheet, PDF (544/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Table 23.6 lists Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock
Output Pin Function Not Selected). Table 23.7 lists P6_4 Pin Functions in Clock Synchronous Serial I/O
Mode.
Note that for a period from when UARTi operating mode is selected to when transmission starts, the TXDi
pin outputs a high-level signal. (If N-channel open-drain output is selected, this pin is in high-impedance
state.)
Table 23.6 Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock
Output Pin Function Not Selected)
Pin Name
TXDi
RXDi
I/O
Output
Input
Input
Function
Serial data output
Serial data input
Input port
CLKi
CTSi/RTSi
Output
Input
Input
Transmit/receive
clock output
Transmit/receive
clock input
CTS input
Output RTS output
Input/
output
i = 0 to 2, 5 to 7
I/O port
Method of Selection
(Outputs dummy data when performing reception only.)
Set the port direction bits sharing pins to 0.
Set the port direction bits to 0. (can be used as an input port
when performing transmission only)
The CKDIR bit in the UiMR register = 0
The CKDIR bit in the UiMR register = 1
Set the port direction bits sharing pins to 0.
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 0
Set the port direction bits sharing pins to 0.
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 1
The CRD bit in the UiC0 register = 1
Table 23.7 P6_4 Pin Functions in Clock Synchronous Serial I/O Mode
Bit Set Value
Pin Function
U1C0 Register
UCON Register
PD6 Register
CRD
CRS
RCSP CLKMD1 CLKMD0
PD6_4
P6_4
CTS1
RTS1
1
-
0
0
-
0
0
0
0
-
0
1
0
0
-
Input: 0, Output: 1
0
-
CTS0 ⁽¹⁾
0
0
1
0
-
0
CLKS1
-
-
-
1 ⁽²⁾
1
-
- indicates either 0 or 1
Notes:
1. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the
CRS bit in the U0C0 register to 1 (RTS0 selected).
2. When the CLKMD1 bit is 1 and the CLKMD0 bit is 0, the following logic levels are output.
•High if the CLKPOL bit in the U1C0 register is 0
•Low if the CLKPOL bit in the U1C0 register is 1
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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