M16C65 Datasheet, PDF (777/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
31. Precautions
31. Precautions
31.1 OFS1 Address and ID Code Storage Address
OFS1 address and ID code storage address are part of flash memory. When writing a program to flash
memory, write an appropriate value to those addresses simultaneously.
In the OFS1 address, the MCU state after reset and the function to prevent rewrite in parallel I/O mode
are selected. The OFS1 address is 0FFFFFh. This is the most significant address of block 0 in program
ROM and upper address of reset vector. Also, the ID code storage address is in block 0 and upper
address of interrupt vector.
When using a compiler to create a program, the reset vector of interrupt vector is created by the compiler
and the OFS1 address or ID code storage address becomes FFh. Write the appropriate value to those
addresses separately. The following is an example when writing to the OFS1 address by an assembler.
ex) Set FEh to the OFS1 address
When using an address control instruction and logical addition:
.org 0FFFCh
RESET:
.lword start | 0FE000000h
When using an address control instruction:
.org 0FFFCh
RESET:
.addr start
.byte 0FEh
31.2 Notes on Noise
Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS
using the shortest and thicker possible wiring. Figure 31.1 shows the Bypass Capacitor Connection.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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