M16C65 Datasheet, PDF (525/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
f1
fOCO-F
OCOSEL0
or
OCOSEL1
f2SIO
1/2
f1SIO
1/8
PCLK1
0
1
1/4
f1SIO or f2SIO
f8SIO
f32SIO
RXDi
RXD polarity
switching circuit
Clock source selection
f1SIO or
f2SIO
f8SIO
f32SIO
CLK1 to CLK0 _CKDIR
00
Internal
01
0
10
1
External
UiBRG
register
1/(n+1)
UART reception _{SMD2 to SMD0}
010, 100, 101, 110
1/16
Clock sync type
001
Reception
control circuit
Receive _Transmit/
clock
receive
unit
UART transmission
1/16 _{010, 100, 101, 110}
Clock sync type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Transmit
clock
CLKi
CTSi/
RTSi
1
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
Clock
(when
synchronous type
external clock is selected)
CKDIR
(when internal clock is selected)
CTS/RTS disabled
CTS/RTS selected
RTSi
1
CRS 0
CTS/RTS disabled
0
CTSi
1
CRD
VSS
n: Value set to the UiBRG register
i = 2, 5 to 7
PCLK1
: Bit in the PCLKR register
SMD2 to SMD0, CKDIR
: Bits in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the UiC0 register
OCOSEL1, OCOSEL0
: Bits in the UCLKSEL0 register
Note :
1. UART2 is an N-channel open-drain output. CMOS output cannot be selected.
Figure 23.3 Block Diagram of UART2, and UART5 to UART7
TXD
polarity
switching
circuit ⁽¹⁾
TXDi
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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