M16C65 Datasheet, PDF (276/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7.3 Interrupt Response Time
Figure 14.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated until the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated until
the executing instruction is completed ((a) in Figure 14.4) and the time during which the interrupt
sequence is executed ((b) in Figure 14.4).
Interrupt request Interrupt request
generated
acknowledged
Instruction
(a)
Interrupt sequence
(b)
Time
Instruction in
interrupt routine
Interrupt response time
(a) The time from when an interrupt request is generated until the instruction currently executing is
completed. The length of this time varies with the instruction being executed. The DIVX instruction
requires the longest time, which is equal to 30 cycles (no wait state, and when the divisor is a register).
(b) The time during which the interrupt sequence is executed. For details, see the table below. Note,
however, that the values in this table must be increased by two cycles for the DBC interrupt and by one
cycle for the address match and single-step interrupts.
Interrupt Vector Address SP Value 16-Bit Bus, No Wait States 8-Bit Bus, No Wait States
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Figure 14.4 Interrupt Response Time
14.7.4 Variation of IPL When Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 14.10 is set in the IPL. Table 14.10 lists the IPL Level Set in IPL When Software or
Special Interrupt is Accepted.
Table 14.10 IPL Level Set in IPL When Software or Special Interrupt is Accepted
Interrupt Source
Watchdog timer, NMI, oscillation stop and re-oscillation detection,
voltage monitor1, voltage monitor 2
Software, address match, DBC, single-step
Level Set in IPL
7
Not changed
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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