M16C65 Datasheet, PDF (686/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
27. A/D Converter
27. A/D Converter
27.1 Introduction
A/D converter consists of one 10-bit successive approximation A/D converter.
Table 27.1 shows A/D Converter Specifications, Figure 27.1 shows an A/D Converter Block Diagram.
Table 27.1 A/D Converter Specifications
Item
A/D conversion
method
Analog input voltage
Operating clock φAD
Resolution
Integral nonlinearity
error
Operation modes
Analog input pins
A/D conversion start
conditions
Conversion rate per
pin
Successive approximation
Specification
0 V to AVCC (VCC1)
f1, f1 divided by 2, f1 divided by 3, f1 divided by 4, f1 divided by 6, f1 divided by 12,
fOCO40M divided by 2, fOCO40M divided by 3, fOCO40M divided by 4,
fOCO40M divided by 6, or fOCO40M divided by 12
10 bits
AVCC = VREF = 5 V
AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB
ANEX0 or ANEX1 input: ±3 LSB
AVCC = VREF = 3.0 V
AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB
ANEX0 or ANEX1 input: ±3 LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
+ 8 pins (AN2_0 to AN2_7)
• Software trigger
The ADST bit in the ADCON0 register is set to 1 (A/D conversion start).
• External trigger (retrigger is enabled)
Input to the ADTRG pin changes from high to low after the ADST bit is set to 1(A/
D conversion start).
Minimum 43 φAD cycles
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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