M16C65 Datasheet, PDF (740/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
30. Flash Memory
30.4 Optional Function Select Address 1 (OFS1)
In an option function select area, the MCU state after reset and the function to prevent rewrite in parallel I/
O mode are selected.
The option function select area is not a special function register (SFR), and therefore cannot be rewritten
by a program. Set a proper value when writing a program in the flash memory. The whole option function
select area is set to FFh when the block including the option function select area is erased.
Optional Function Select Address 1
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
OFS1
Address
FFFFFh
Factory Setting
FFh
Bit Symbol
Bit Name
Function
RW
0 : Watchdog timer starts automatically
WDTON
Watchdog timer start select bit
after reset.
1 : Watchdog timer is in a stopped state
RW
after reset.
—
(b1)
Reserved bit
Set to 1.
RW
ROMCR ROM code protect cancel bit
0 : ROM code protection cancelled.
1 : ROMCP1 bit enabled.
RW
ROMCP1 ROM code protect bit
0 : ROM code protection enabled.
1 : ROM code protection disabled.
RW
—
(b4)
Reserved bit
Set to 1.
RW
VDSEL1 Vdet0 select bit 1
0 : 2.85 V (Vdet0_2)
1 : 1.90 V (Vdet0_0)
RW
0 : Voltage monitor 0 reset enabled
LVDAS
Voltage detection 0 circuit
start bit
after hardware reset.
1 : Voltage monitor 0 reset disabled
RW
after hardware reset.
0 : Count source protection mode
CSPROINI
After-reset count source
protection mode select bit
enabled after reset.
1 : Count source protection mode
RW
disabled after reset.
ROMCR (ROM Code Protect Disable Bit) (b2)
ROMCP1 (ROM Code Protect Bit) (b3)
These bits are used to inhibit the flash memory from being read or rewritten during parallel I/O mode.
Table 30.5 ROM Code Protect
Bit Setting
ROMCR bit
ROMCP1 bit
0
0
0
1
1
0
1
1
ROM Code Protect
Disabled
Enabled
Disabled
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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