M16C65 Datasheet, PDF (212/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
(1) Separate Bus, Three Wait States (1φ + 3φ)
Bus cycle = 4φ
BCLK
Address
CSi
Data
RD
WR, WRL, WRH
A
WD
Bus cycle = 4φ
A
RD
(Note 1)
(2) Multiplexed Bus, One or Two Wait States (1φ + 2φ)
Bus cycle = 3φ
BCLK
Address
Address/Data
A
A
WD
ALE
CSi
RD
WR, WRL, WRH
Bus cycle = 3φ
A
A
RD
(Note 1)
(3) Multiplexed Bus, Three Wait States (1φ + 3φ)
Bus cycle = 4φ
BCLK
Address
A
Address/Data
A
WD
ALE
CSi
RD
WR, WRL, WRH
Bus cycle = 4φ
A
A
RD
(Note 1)
i = 0 to 3
A : Address RD : Read data (input) WD : Write data (output)
Note:
1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level.
Figure 11.7 Typical Bus Timings Using Software Wait States (2/4)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 177 of 791