M16C65 Datasheet, PDF (311/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
(1) Transfers are performed in 8-bit or 16-bit units, and source of transfer is an even address.
BCLK
Address
bus
RD signal
WR signal
Data bus
CPU use
CPU use
Source
Destination
Dummy
cycle
Source
Destination
Dummy
cycle
CPU use
CPU use
(2) Transfers are performed in 16-bit units, and the source address of transfer is an odd address.
BCLK
Address
bus
RD signal
WR signal
Data bus
CPU use
CPU use
Source Source + 1
Destination
Dummy
cycle
Source Source + 1
Destination
Dummy
cycle
CPU use
CPU use
(3) Source read cycle under condition (1) with one wait state inserted
BCLK
Address
bus
RD signal
CPU use
Source
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) Source read cycle under condition (2) with one wait state inserted
BCLK
Address
bus
RD signal
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
WR signal
Data bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note :
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 16.2 Transfer Cycles for Source Read Operations
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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