M16C65 Datasheet, PDF (137/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8.2.1 Processor Mode Register 0 (PM0)
8. Clock Generator
Processor Mode Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Bit Symbol
Address
0004h
Bit Name
After Reset
0000 0000b (CNVSS pin is held low)
0000 0011b (CNVSS pin is held high)
Function
RW
PM00
PM01
Processor mode bit
b1 b0
RW
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Do not set
1 1 : Microprocessor mode
RW
PM02 R/W mode select bit
0 : RD, BHE, WR
1 : RD, WRH, WRL
RW
PM03 Software reset bit
Setting this bit to 1 resets the MCU.
Read as 0.
RW
PM04
b5 b4
0 0 : Multiplexed bus is unused
RW
Multiplexed bus space select
(separate bus in the entire CS space)
bit
0 1 : Allocated to CS2 space
PM05
1 0 : Allocated to CS1 space
RW
1 1 : Allocated to the entire CS space
PM06
Port P4_0 to P4_3 function
select bit
0 : Address output
1 : Port function (address is not output)
RW
0 : BCLK is output
PM07 BCLK output disable bit
1 : BCLK is not output
RW
(pin is left in high-impedance)
Write to the PM0 register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
Bits PM01 to PM00 do not change at software reset, watchdog timer reset, oscillation stop detection
reset, voltage monitor 1 reset, or voltage monitor 2 reset.
PM07 (BCLK Output Disable Bit) (b7)
This bit is enabled in memory expansion mode and microprocessor mode. A clock with the same
frequency as that of the CPU clock is output as the BCLK signal from the BCLK pin.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 102 of 791