SH7615 Datasheet, PDF (90/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and
conditional branches occur in accordance with its true or false status. The number of instructions
modifying the T bit is kept to a minimum to improve the processing speed.
Table 2.8 T Bit
SH7615 CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
#–1,R0
CMP/EQ #0,R0
BT
TRGET
Description
Example of Conventional CPU
T bit is set when R0 ≥ R1.
CMP.W R1,R0
The program branches to TRGET0 BGE TRGET0
when R0 ≥ R1.
The program branches to TRGET1 BLT
when R0 < R1
TRGET1
T bit is not changed by ADD. T bit SUB.W #1,R0
is set when R0 = 0. The program _{BEQ TRGET}
branches when R0 = 0
Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate
data is not input in instruction codes but is stored in a memory table. An immediate data transfer
instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.
Table 2.9 Immediate Data Accessing
Classification SH7615 CPU
8-bit immediate MOV #H'12,R0
16-bit immediate MOV.W @(disp,PC),R0
........
.DATA.W H'1234
32-bit immediate MOV.L @(disp,PC),R0
........
.DATA.L H'12345678
Note: @(disp, PC) accesses the immediate data.
Example of Conventional CPU
MOV.B #H'12,R0
MOV.W #H'1234,R0
MOV.L #H'12345678,R0
Rev. 2.00, 03/05, page 52 of 884