SH7615 Datasheet, PDF (661/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

In serial transmission, the SCIF operates as described below.
1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data
from SCFTDR to the transmit shift register (SCTSR), and starts transmitting. Check that the
TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to
SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set
number)}.
2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit
operations are performed continually until there is no transmit data left in SCFTDR. If the
number of data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO
control register (SCFCR) during transmission, the TDFE flag is set. If the TIE bit setting in the
serial control register (SCSCR) is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is
requested.
When clock output mode has been set, the SCIF outputs eight serial clock pulses for one unit
of data.
When use of an external clock has been specified, data is output in synchronization with the
input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) or MSB (bit 7)
according to the setting of the TLM bit in the serial status 2 register (SC2SSR).
3. The SCIF checks for transmit data in SCFTDR at the timing for sending the last bit. If there is
transmit data in SCFTDR, it is transferred to SCTSR and then serial transmission of the next
frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in the serial
status 1 register (SC1SSR), the last bit is sent, and then the transmit data pin (TxD) holds its
state.
4. After completion of serial transmission, the SCK pin is fixed high.
Figure 14.19 shows an example of SCIF operation in transmission.
Rev. 2.00, 03/05, page 623 of 884