SH7615 Datasheet, PDF (334/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Setting
Output
SZ AMX2 AMX1 AMX0 Timing A1–A8 A9
External Address Pins
A10 A11 A12 A13 A14 A15
01
0
0
Column A1–A8 A9
address
A10 LH^*1 A12 A21^*3 A22^*2 A15
Row
A9–A16 A17 A18 A19 A20 A21^*3 A22^*2 A23
address
00
1
1
Column A1–A8 L/H^*1 A18^*2 A11 A12 A13 A14 A15
address
01
1
1
Row A9–A16 A17 A18^*2 A19 A20 A21 A22 A23
address
Column A1–A8 L/H^*1 A17^*2 A11 A12 A13 A14 A15
address
Row
A9–A16 A16 A17^*2 A19 A20 A21 A22 A23
address
Notes: AMX2 to AMX0 setting 110 is reserved and must not be used. When SZ = 0, AMX2 to
AMX0 settings 001, 010, and 101 are also reserved and must not be used.
1. L/H is a bit used to specify commands. It is fixed at L or H according to the access
mode.
2. Bank address specification.
3. Bank address specification when using four banks.
7.5.3 Burst Reads
Figure 7.19 (a) and (b) show the timing charts for burst reads. In the following example, 2
synchronous DRAMs of 256k × 16 bits are connected, the data width is 32 bits and the burst
length is 4. After a Tr cycle that performs ACTV command output, a READA command is issued
in the Tc cycle, read data is accepted in cycles Td1 to Td4, and the end of the read sequence is
waited for in the Tde cycle. One Tde cycle is issued when Iφ:Eφ ≠ 1:1, and two cycles when Iφ:Eφ
= 1:1. Tap is a cycle for waiting for the completion of the auto-precharge based on the READA
command within the synchronous DRAM. During this period, no new access commands are
issued to the same bank. Accesses of the other bank of the synchronous DRAM by another CS
space are possible. Depending on the TRP1, TRP0 specification in MCR, the chip determines the
number of Tap cycles and does not issue a command to the same bank during that period.
Figure 7.19 (a) and (b) show examples of the basic cycle. Because a slower synchronous DRAM is
connected, setting WCR1 and MCR bits can extend the cycle. The number of cycles from the
ACTV command output cycle Tr to the READA command output cycle Tc can be specified by
bits RCD1 and RCD0 in MCR. 00 specifies 1 cycle, 01 specifies 2 cycles, and 10 specifies 3
cycles. For 2 or 3 cycles, a NOP command issue cycle Trw for the synchronous DRAM is inserted
between the Tr cycle and the Tc cycle. The number of cycles between the READA command
output cycle Tc and the initial read data fetch cycle Td1 can be specified between 1 cycle and 4
cycles using the W21/W20 and W31/W30 bits in WCR1. The number of cycles at this time
Rev. 2.00, 03/05, page 296 of 884