SH7615 Datasheet, PDF(343/925 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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SH7615 Datasheet, PDF (343/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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When a single write is performed in burst write mode, the synchronous DRAM setting is for a

burst length of 4. After data is written in Tc1, empty writes are performed in Tc2, Tc3, and Tc4 by

driving the DQMxx signal high.

These empty cycles increase the memory access time and tend to reduce program execution speed

and DMA transfer speed. Therefore, unnecessary cache-through area accesses should be avoided,

and copy-back should be selected for the cache setting. Also, in DMA transfer, it is important to

use a data structure that allows transfer in 16-bit units.

Tr

CKIO

A24âA11

A10

A9âA1

CS2 or CS3

RAS

CAS

RD/WR

DQMxx

D31âD0

DACKn*

Tc1

Tc2

Tc3

Tc4

Trwl

Tap

Note: * DACKn waveform when active-low is specified.

Figure 7.23 (a) Basic Burst Write Timing (Auto-Precharge) Except tEcyc:tPcyc 1:1

Rev. 2.00, 03/05, page 305 of 884

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