SH7615 Datasheet, PDF (596/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

13.3.2 Operation in Interval Timer Mode
IT To use the WDT as an interval timer, clear WT/ to 0 and set TME to 1 in WTCSR. An interval
timer interrupt (ITI) is generated each time the watchdog timer counter (WTCNT) overflows. This
function can be used to generate interval timer interrupts at regular intervals (figure 13.5).
WTCNT value
H'FF
Overflow
Overflow
Overflow
Overflow
H'00
WT/IT = 0
ITI
ITI
ITI
TME = 1
ITI: Interval timer interrupt request generation
Figure 13.5 Operation in Interval Timer Mode
Time
ITI
13.3.3 Operation when Standby Mode is Cleared
The watchdog timer has a special function to clear standby mode with an NMI interrupt. When
using standby mode, set the WDT as described below.
Transition to Standby Mode: The TME bit in WTCSR must be cleared to 0 to stop the watchdog
timer counter before it enters standby mode. The chip cannot enter standby mode while the TME
bit is set to 1. Set bits CKS2 to CKS0 in WTCSR so that the counter overflow interval is equal to
or longer than the oscillation settling time. See section 21, Electrical Characteristics, for the
oscillation settling time.
Recovery from Standby Mode: When an NMI request signal is received in standby mode the
clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits
CKS2 to CKS0 before standby mode was entered. When WTCNT overflows (changes from H'FF
to H'00) the system clock (φ) is presumed to be stable and usable; clock signals are supplied to the
entire chip and standby mode ends.
For details on standby mode, see section 20, Power Down Modes.
Rev. 2.00, 03/05, page 558 of 884