SH7615 Datasheet, PDF (183/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.1.3 Input/Output Pins
Table 5.1 shows the INTC pin configuration.
Table 5.1 Pin Configuration
Name
Abbreviation I/O Function
Nonmaskable interrupt input pin NMI
Input Input of nonmaskable interrupt request
signal
Level request interrupt input pins to IRL3 IRL0 Input Input of maskable interrupt request
signals
Interrupt acceptance level output A3 to A0
pins
Output In external vector mode, output an
interrupt level signal when an IRL/IRQ
interrupt is accepted
External vector fetch pin
IVECF
Output Indicates external vector read cycle
External vector number input pins D7 to D0
Input Input external vector number
5.1.4 Register Configuration
The INTC has the 31 registers shown in table 5.2. These registers perform various INTC functions
including setting interrupt priority, and controlling external interrupt input signal detection.
Table 5.2 Register Configuration
Name
Abbr.
Interrupt priority register setting register A IPRA
Interrupt priority register setting register B IPRB
Interrupt priority register setting register C IPRC
Interrupt priority register setting register D IPRD
Interrupt priority register setting register E IPRE
Vector number setting register A
Vector number setting register B^*3
VCRA
VCRB
Vector number setting register C
VCRC
Vector number setting register D
VCRD
Vector number setting register E
VCRE
Vector number setting register F
VCRF
Vector number setting register G
VCRG
Initial
R/W Value
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
Address
Access
Size
H'FFFFFEE2 8, 16
H'FFFFFE60 8, 16
H'FFFFFEE6 8, 16
H'FFFFFE40 8, 16
H'FFFFFEC0 8, 16
H'FFFFFE62 8, 16
H'FFFFFE64 8, 16
H'FFFFFE66 8, 16
H'FFFFFE68 8, 16
H'FFFFFE42 8, 16
H'FFFFFE44 8, 16
H'FFFFFE46 8, 16
Rev. 2.00, 03/05, page 145 of 884