SH7615 Datasheet, PDF (795/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

17.6 Usage Notes
• A reset must always be executed by driving the TRST signal to 0, regardless of whether or not
the H-UDI is to be activated. TRST must be held low for 20 TCK clock cycles. For details, see
section 21, Electrical Characteristics.
• The registers are not initialized in standby mode. If TRST is set to 0 in standby mode,
IDCODE mode will be entered.
• The frequency of TCK must be lower than that of the peripheral module clock (Pφ). For
details, see section 21, Electrical Characteristics.
• In data transfer, data input/output starts with the LSB. Figure 17.6 shows serial data
input/output.
• When data that exceeds the number of bits of the register connected between TDI and TDO is
serially transferred, the serial data that exceeds the number of register bits and output from
TDO is the same as that input from TDI.
• If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer
should then be retried, regardless of the transfer operation.
• TDO is output at the falling edge of TCK when one of six instructions defined in IEEE1149.1
is selected. Otherwise, it is output at the rising edge of TCK.
• SDIR and SDSR serial data input/output
In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and
bits 0 to 15 of SDIR are output in that order from TDO.
In Update-IR, data input from TDI is written to SDIR, but not to SDSR.
TDI
TDI
Shift register
Bit 31
Bit 15
.
SDIR
..
SDIR
Bit 16
Bit 0
Bit 15
Bit 15
SDSR
Bit 0
..
.
Bit 0
SDSR
Shift register
TDI
input
data
Bit 31
...
Bit 16
Bit 15
Bit 15
Bit 0
SDIR
Bit 0
SDSR
TDO
Capture-IR
TDO
Update-IR
Figure 17.6 Serial Data Input/Output (1)
Rev. 2.00, 03/05, page 757 of 884