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SH7615 Datasheet, PDF (534/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series
Address
Mode Transfer Range
Request Mode*3
Bus Transfer
Mode*7 Size (Byte)
Dual
Between internal memory and
internal peripheral module
External
Automatic
B/C
1/2/4*4
B/C
1/2/4*4
Internal peripheral module*2 C
1/2/4*4
Between internal memory and
external memory*6
External
Automatic
B/C
1/2/4/16*8
B/C
1/2/4/16
Internal peripheral module*1 C
1/2/4
Between internal peripheral
modules
External
Automatic
B/C
1/2/4*4
B/C
1/2/4*4
Internal peripheral module*2 C
1/2/4*4
Notes: B: Burst mode
C: Cycle steal mode
1. For on-chip peripheral module requests, do not specify SCIF and SIO as a transfer
request source.
2. When the transfer request source is SCIF or SIO, the transfer source or transfer
destination must be SCIF and SIO, respectively.
3. When the request mode is set to internal peripheral module request, set the DS bit and
the DL bit of CHCR0 and CHCR1 to 1 and 0, respectively (detection at the falling edge
of DREQn). In addition, the bus mode can only be set to cycle-steal mode.
4. Specify the access size that is allowed by the internal peripheral-module registers,
which are a transfer source or a transfer destination.
5. When transferring data from internal memory to a memory mapped external device, set
DACKn to write-time output. When transferring from a memory mapped external device
to internal memory, set DACKn to read-time output.
6. When transferring data from internal memory to external memory, set DACKn to write-
time output. When transferring from external memory to internal memory, set DACKn to
read-time output.
7. When B (burst mode) is set in the external request mode, set the DS bits of CHCR0
and CHCR1 to 1 (edge detection). If they are set to 0 (level detection), operation cannot
be guaranteed.
8. Transfer in units of 16 bytes is enabled only when edge detection has been specified. If
transfer is attempted in units of 16 bytes when level detection has been specified,
operation cannot be guaranteed.
Rev. 2.00, 03/05, page 496 of 884