SH7615 Datasheet, PDF (72/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

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0
R0^*1
R1
R2, [As]^*3
R3, [As]^*3
R4, [As, Ax]^*3
R5, [As, Ax]^*3
R6, [Ay]^*3
R7, [Ay]^*3
R8, [Ix, Is]^*3
R9, [Iy]^*3
R10
R11
R12
R13
R14
R15, SP ^*2
Notes:
1. R0 also functions as an index register in the indirect indexed register
addressing mode and indirect indexed GBR addressing mode. In some
instructions, only the R0 functions as a source register or destination register.
2. R15 functions as a hardware stack pointer (SP) during exception processing.
3. Used as memory address registers, memory index registers with DSP type
instructions.
Figure 2.1 General Register Configuration
With the assembler, symbol names are used for R2, R3 ... R9. If it is wished to use a name that
makes clear the role of a register for DSP type instructions, a different register name (alias) can be
used. This is written in the following manner for the assembler.
Ix: .REG (R8)
Rev. 2.00, 03/05, page 34 of 884