SH7615 Datasheet, PDF (426/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.2.5 MAC Address High Register (MAHR)
Bit:
Initial value:
R/W:
31
MA47
0
R/W
30
MA46
0
R/W
29
MA45
0
R/W
28
MA44
0
R/W
27
MA43
0
R/W
26
MA42
0
R/W
25
MA41
0
R/W
24
MA40
0
R/W
Bit:
Initial value:
R/W:
23
MA39
0
R/W
22
MA38
0
R/W
21
MA37
0
R/W
20
MA36
0
R/W
19
MA35
0
R/W
18
MA34
0
R/W
17
MA33
0
R/W
16
MA32
0
R/W
Bit:
Initial value:
R/W:
15
MA31
0
R/W
14
MA30
0
R/W
13
MA29
0
R/W
12
MA28
0
R/W
11
MA27
0
R/W
10
MA26
0
R/W
9
MA25
0
R/W
8
MA24
0
R/W
Bit:
Initial value:
R/W:
7
MA23
0
R/W
6
MA22
0
R/W
5
MA21
0
R/W
4
MA20
0
R/W
3
MA19
0
R/W
2
MA18
0
R/W
1
MA17
0
R/W
0
MA16
0
R/W
The upper 32 bits of the 48-bit MAC address are set in MARH. The setting in this register is
normally made in the initialization process after a reset.
Note: The MAC address setting must not be changed while the transmitter and receiver are
enabled. First return the EtherC and E-DMAC modules to their initial state by means of
the SWR bit in the E-DMAC mode register (EDMR), then make the new setting.
Bits 31 to 0—MAC Address Bits 47 to 16 (MA47 to MA16): Used to set the upper 32 bits of the
MAC address.
Note: If the MAC address to be set in the SH7615 is 01-23-45-67-89-AB (hexadecimal), the
value set in this register is H'01234567.
Rev. 2.00, 03/05, page 388 of 884