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| SH7615 Datasheet, PDF (854/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series | |||
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Tp
Tpw
Tr
Tc
Td1
Tde
CKIO
Address
upper bits
Address
lower bits
BS
CSn
RD/WR
tRWD
RD
WEn â
DQMxx
D31âD0
DACKn
WAIT
RAS
tRASD1
tRASD1
CAS â
OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.22 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access,
TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle)
Rev. 2.00, 03/05, page 816 of 884
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