SH7615 Datasheet, PDF (796/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• SDDRH and SDDRL serial data input/output
(1) In H-UDI interrupt mode, before SDTRF = 1 is read from TDO when an H-UDI interrupt is generated,
SDSR and SDIR are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDSR
and bits 0 to 15 of SDIR are output in that order from TDO.
In Update-DR, TDI input data is not written to any register.
TDI
Shift register
Bit 31
Bit 15
SDIR
...
SDIR
Bit 16
Bit 0
Bit 15
Bit 15
SDSR
Bit 0
..
.
Bit 0
SDSR
TDO
Capture-DR
(2) In H-UDI interrupt mode, after SDTRF = 1 is read from TDO when an H-UDI interrupt is generated,
SDDRH and SDDRL are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of
SDDRL and bits 0 to 15 of SDDRH are output in that order from TDO.
Data input from TDI is written to SDDRH and SDDRL in Update-DR.
TDI
TDI
Shift register
Bit 31
SDDRH
.
..
Bit 16
Bit 15
.
SDDRL
..
Bit 0
Bit 15
SDDRH
Bit 0
Bit 15
SDDRL
Bit 0
Shift register
TDI
input
data
Bit 31
.
..
Bit 16
Bit 15
.
..
Bit 0
Bit 15
SDDRH
Bit 0
Bit 15
SDDRL
Bit 0
TDO
Capture-DR
TDO
Update-DR
Figure 17.6 Serial Data Input/Output (2)
Rev. 2.00, 03/05, page 758 of 884