SH7615 Datasheet, PDF (232/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 5.8 Interrupt Response Time
Number of States
Peripheral Module
Item
NMI
IRL/IRQ
A
B
Notes
Compare identified
interrupt priority with SR
mask level
2.0 × Icyc
0.5 × Icyc
+ 1.0 × Ecyc
+ 1.5 × Pcyc
0.5 × Icyc
+ 1.0 × Pcyc
1.0 × Pcyc
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
X (≥ 0)
X (≥ 0)
The longest
sequence is for
interrupt or address-
error exception
handling (X = 4.0 ×
Icyc + m1 + m2 +
m3 + m4). If an
interrupt-making
instruction follows,
however, the time
may be even longer
during repeat
instruction
execution
Time from interrupt
exception handling (SR
and PC saves and vector
address fetch) until fetch of
first instruction of exception
service routine starts
5.0 × Icyc
+ m1 + m2
+ m3
5.0 × Icyc
+ m1 + m2
+ m3
5.0 × Icyc
+ m1 + m2
+ m3
5.0 × Icyc
+ m1 + m2
+ m3
Response time
Total:
X + 7.0 × Icyc
+ m1 + m2
+ m3
X + 5.5 × Icyc
+ 1.0 × Ecyc
+ 1.5 × Pcyc
+ m1 + m2
+ m3
X + 5.5 × Icyc
+ 1.0 × Pcyc
+ m1 + m2
+ m3
X + 5.0 × Icyc
+ 1.0 × Pcyc
+ m1 + m2
+ m3
Minimum: 10
11
9.5
9
Iφ:Eφ:Pφ = 1:1:1
Maximum: 11 + 2 (m1
+ m2 + m3)
+ m4
19.5 + 2 (m1 13.5 + 2 (m1 13.0 + 2 (m1 Iφ:Eφ:Pφ = 1:1/4:1/4
+ m2 + m3) + m2 + m3) + m2 + m3)
+ m4
+ m4
+ m4
Note:
m1 to m4 are the number of states needed for the following memory accesses
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch of first instruction of interrupt service routine
Icyc: Iφ cycle time
Ecyc: Eφ cycle time
Pcyc: Pφ cycle time
Peripheral modules A: DMAC, REF (BSC)
Peripheral modules B: WDT, FRT, TPU, SCIF, SIO, E-DMAC
Rev. 2.00, 03/05, page 194 of 884