SH7615 Datasheet, PDF (224/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Register
Vector number setting register R
Vector number setting register S
Vector number setting register T
Vector number setting register U
Bits
14 to 8
6 to 0
Receive overrun error interrupt Transmit underrun error
(SIO1)
interrupt (SIO1)
Receive-data-full interrupt
(SIO1)
Transmit-data-empty interrupt
(SIO1)
Receive overrun error interrupt Transmit underrun error
(SIO2)
interrupt (SIO2)
Receive-data-full interrupt
(SIO2)
Transmit-data-empty interrupt
(SIO2)
As table 5.6 shows, two on-chip peripheral module interrupts are assigned to each register. Set the
vector numbers by setting the corresponding 7-bit groups (bits 14 to 8 and bits 6 to 0) with values
in the range of H'00 (0000000) to H'7F (1111111). H'00 is vector number 0 (the lowest); H'7F is
vector number 127 (the highest). The vector table address is calculated by the following equation.
Vector table address = VBR + (vector number × 4)
A reset initializes a vector number setting register to H'0000. They are not initialized in standby
mode.
Table 5.7 Interrupt Request Sources and Vector Number Setting Registers (2)
Register
Vector number setting register DMA0
(VCRDMA0)
Vector number setting register DMA1
(VCRDMA1)
Setting Function
Channel 0 transfer end interrupt for DMAC
Channel 1 transfer end interrupt for DMAC
As shown in table 5.7 the vector numbers for direct memory access controller transfer-end
interrupts are set in VCRDMA0 and VCRDMA1. See sections 11, Direct Memory Access
Controller (DMAC), for more details.
Rev. 2.00, 03/05, page 186 of 884