SH7615 Datasheet, PDF (104/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Instruction Formats
Destination
Source Operand Operand
Example
d format
15
xxxx xxxx
0
dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
@(disp,GBR),R0
displacement
R0(Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement
R0 (Direct register) MOVA
@(disp,PC),R0
dddddddd: PC —
relative
BF label
dddddddddddd: —
PC relative
BRA label
(label=disp+PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
15
0
xxxx xxxx i i i i i i i i
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii:
Immediate
iiiiiiii:
Immediate
iiiiiiii:
Immediate
iiiiiiii:
Immediate
Indirect indexed AND.B
GBR
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0
—
TRAPA #imm
nnnn: Direct
register
ADD #imm,Rn
Note: * In multiply/accumulate instructions, nnnn is the source register.
Rev. 2.00, 03/05, page 66 of 884