SH7615 Datasheet, PDF (219/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.3.24 Vector Number Setting Register R (VCRR)
Vector number setting register R (VCRR) is a 16-bit read/write register that sets the serial I/O 1
(SIO1) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0 to
127).
VCRR is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— RER1V6 RER1V5 RER1V4 RER1V3 RER1V2 RER1V1 RER1V0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
— TER1V6 TER1V5 TER1V4 TER1V3 TER1V2 TER1V1 TER1V0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Serial I/O 1 (SIO1) Receive Overrun Error Interrupt Vector Number 6 to 0
(RER1V6 to RER1V0): These bits set the vector number for the serial I/O 1 (SIO1) receive
overrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Serial I/O 1 (SIO1) Transmit Underrun Error Interrupt Vector Number 6 to 0
(TER1V6 to TER1V0): These bits set the vector number for the serial I/O 1 (SIO1) transmit
underrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00, 03/05, page 181 of 884